Dynamic threshold voltage MOS transistor fitted with a current limiter

ABSTRACT

The invention concerns a semi-conductor device comprising on a substrate: 
     a first dynamic threshold voltage MOS transistor ( 10 ), with a gate ( 116 ), and a channel ( 111 ) of a first conductivity type, and 
     a current limiter means ( 20 ) connected between the gate and the channel of said first transistor. 
     In accordance with the invention, this first transistor is fitted with a first doped zone ( 160 ) of the first conductivity type, connected to the channel, and the current limiter means comprises a second doped zone ( 124 ) of a second conductivity type, placed against the first doped zone and electrically connected to the first zone by an ohmic connection. 
     Application to the manufacture of CMOS circuits.

This application is a national phase of PCT/FR00/00268, andInternational Application No. 99 01369, which was filed on Feb. 5, 1999,and was not published in English.

TECHNICAL FIELD

This invention concerns a dynamic threshold voltage MOS transistor(insulated gate Transistor) fitted with an integrated current limiter.This device is intended in particular to be made on an SOI (silicon oninsulator) type substrate, in other words a substrate having a thinsurface layer of silicon insulated by an underlying layer of oxide.

The invention also concerns a process for making such a device in aparticularly compact form with a view to integrating it into a circuit.

The invention finds applications particularly in the manufacture of CMOScircuits operating with very low supply voltages such as for examplemicro-processors or digital signal processors (DSP).

PRIOR ART

The prior art is shown particularly in documents (1), (2), (3) and (4)mentioned below and the references for which are given at the end ofthis description.

A usual MOS transistor may be considered as being made up of twointrinsic components. The first component is the MOS transistor itself,in which the current, controlled by the gate, flows between the drainand the source, and in which the substrate is subject to fixedpolarisation. The second component is a bipolar parasitic transistor forwhich the drain and the source act as transmitter and collector, and thesubstrate acts as the base.

Document (1) proposes the simultaneous activation of the MOS componentand the bipolar component so as to increase the total current suppliedby the device, and to do this by connecting the transistor gate to itssubstrate. Such a device is however little used on account of thesignificant increase in static current related to the operation of thebipolar component. Indeed, minimal static current is generally requiredin CMOS circuits.

Document (2) proposes a hybrid mode of operation of the MOS and showsthat, by means of the connection between the gate and the substrate, thethreshold voltage of the MOS may be lowered and the transistorcharacteristic gradient under the threshold may be improved at lowvoltage, in other words before the bipolar transistor is activated. Thisoperational principle has given rise to the dynamic threshold voltagetransistor described in document (3) “Dynamic Threshold Voltage MOSFET”or “DTMOS”.

The symbolic electrical diagram of a dynamic threshold voltage MOStransistor (DTMOS) is shown in the appended FIG. 1.

The transistor 10 comprises, like any MOS transistor, a drain terminal12, connected to a source terminal 14 by a channel, and a gate terminal16 to control the current passing through the channel.

Moreover, an electrical connection 18 is established between the gateand the substrate. In the figure a substrate contact terminal to whichthe electrical connection 18 is connected is identified with thereference 11.

The threshold voltage V_(t) of a MOS transistor depends on the voltageapplied on its substrate.

As shown in document (4), the voltage V_(t) may be expressed by thefollowing relation.

V _(t) =V _(fb)+2φ_(f)+γ{square root over (2φ_(f) −V _(bs))}

In this expression, V_(fb) is the flat band voltage, φ_(f) is the Fermipotential, γ is the substrate effect coefficient and V_(bs) is thepotential difference applied between the substrate and the transistorsource.

When the gate is connected to the substrate as is the case for theDTMOS, the voltage applied to the gate is also applied to the substrate.The threshold voltage is then dependent on the voltage applied to thegate, which justifies the term “dynamic threshold voltage transistor”.

During normal operation, in respect of an NMOS transistor, taken here byway of illustration, the polarisation applied to the gate is positiverelative to the source. It brings about the forward bias of the junctionexisting between substrate and source, and possibly the forward bias ofthe junction between substrate and drain (depending on the polarisationapplied to the drain). If high voltage is applied to the gate, the samevoltage applied to the substrate causes a significant current to pass inthe junction. This contributes to the increase in total static currentin a circuit fitted with the DTMOS component.

The maximum acceptable current for a DTMOS in SOI technology is about0.6 V, so as to limit this junction current to approximately 100 pA permicrometer of transistor width. Using a DTMOS at a higher supply voltagerequires a device to be inserted which enables the junction current tobe reduced. Such a device is inserted between the gate and the substrateand is called a current limiter. Reference may be made on this subjectto document (3).

The current limiter is a second MOS transistor for which differentconfigurations of polarisation are conceivable.

A first proposed configuration is shown in the appended FIG. 2.

FIG. 2 shows the MOS transistor 10 of FIG. 1, which is fitted with acurrent limiter in the form of a second MOS transistor 20 insertedbetween the gate terminal 16 and the substrate terminal 11.

The gate 26 of the second transistor is polarised at the supply voltagein the case of an NMOS transistor and is polarised at the earth in thecase of a PMOS transistor.

Another possible polarisation configuration of the second transistor isshown in the appended FIG. 3.

It is distinguished from the configuration in FIG. 2 essentially in thatthe gate 26 of the second transistor 20 is henceforth connected to itssource.

It should be specified that the second transistor 20 is a conventionaltransistor providing no access to the substrate. Its substrate isfloating.

One essential difficulty related to the manufacture of a deviceaccording to the diagrams in FIG. 2 or 3 lies in the fact that makingthe limiter transistor and the connections with the first transistor isincompatible with the requirements for reducing the sizes of components.

Indeed, the search for an ever greater integration density of componentsdoes not allow the electrical diagram of the devices mentioned above tobe transcribed directly in an integrated version.

DISCLOSURE OF THE INVENTION

The purpose of the present invention is to propose a DTMOS transistordevice with current limiter, which. does not have the difficulties aboveand is able to be made in the form of an integrated circuit.

A particular purpose is to propose a device of this type which allowsthe number and range of connections required between the transistors tobe reduced, so as to allow it to be made compactly.

Another purpose is propose a particularly cost-effective process formanufacturing the device.

To fulfil these purposes, a more precise object of the invention is asemi-conductor device, comprising on a substrate:

a first dynamic threshold voltage MOS transistor with a gate, and achannel of a first conductivity type, and

a current limiter means connected between the gate and the channel ofsaid first MOS transistor.

In accordance with the invention, the first MOS transistor is fittedwith a first doped zone of the first conductivity type, connected to thechannel, and the current limiter means comprises a second doped zone ofa second conductivity type, placed against the first doped zone andelectrically connected to the first doped zone by an ohmic connectionpath.

In terms of the invention, the ohmic connection between the first andsecond doped zones of a simple connection is distinguished by physicalcontact resulting from the juxtaposition of these areas.

The ohmic connection may be made, for example, by a layer ofelectrically conductive material, such as a layer of silicide, whichconnects the first and second doped zones to each other.

In a particular embodiment of the device of the invention, the currentlimiter means may be a second MOS transistor. In this case, the seconddoped zone and a third doped zone of the same conductivity type as thesecond doped zone may form the source and drain of said transistor.

Between the source and drain of the second transistor, in other wordsbetween the second and third doped zones, is a channel area of anopposite conductivity type, that is to the first conductivity type. Thedoping concentration of the channel is however lower than that of thesource and drain.

According to different configurations of polarisation, the gate of thesecond transistor may be connected to a gate polarisation terminal or tothe second doped zone, in other words to the source of the secondtransistor.

In this second case, a common connection terminal may be provided bothfor the gate and the second doped zone.

The third doped zone, in other words here the drain of the secondtransistor, may be connected to the gate of the first transistor.

In another particular embodiment of the invention device, the currentlimiter means may further be a diode. The second doped zone and a thirddoped zone, of an opposite conductivity type to that of the second dopedzone, then form the terminals of the diode.

While the second and third doped zones have a relatively high dopingconcentration, they may be separated by a fourth doped zone having alower doping concentration.

While the second and third doped zones are of an opposite conductivitytype, the fourth zone may be either of the conductivity type of thesecond zone, or of that of the third zone.

The effect of the fourth zone is thus to extend one of the second orthird doped zones so as to form a junction of the P⁺N or N⁺P type.

Just as in the previously described embodiment, the third doped zone maybe connected to the gate of the first MOS transistor.

Furthermore, according to a particular embodiment of the diode, thelatter may be fitted with a gate extending over the fourth doped zone.This gate does not really have an electrical function but may act, aswill emerge in the following description, as an implantation mask of thesecond and third doped zones, in order to preserve the fourth dopedzone.

The diode gate may be left floating or may be connected to one of thediode terminals, in other words to one of the second and third dopedzones.

The invention also concerns a process for manufacturing a device such aspreviously described.

Where the device comprises a current limiter in the form of an MOStransistor, the process comprises the following successive stages:

a) preparation in a substrate of an active zone, intended to receive thefirst and second transistors and having a first conductivity type,

b) formation of a first and a second gate above the active zone,corresponding to the first and second transistors respectively, thegates being separated from the substrate by a gate insulator andcovering channel areas of the first and second transistors respectively,

c) formation of first and second source and drain areas of a secondconductivity type opposite to the first conductivity type, correspondingto the first and second transistors respectively, by self-aligned ionimplantation on the first and second gates, and formation of the firstdoped zone of the first conductivity type, in contact with the channelof the first transistor and adjacent to one of the source and drainareas of the second transistor, by self-aligned ion implantation on thegate of the first transistor,

d) formation of a conductive layer in electrical contact with the firstdoped zone and one of the source and drain areas of the secondtransistor adjacent to said first doped zone, so as to connect themelectrically.

By self-aligned implantation on a gate is understood an implantationduring which the gate is used at least partially as an implantation maskor as a part of an implantation mask.

The process may be completed, after stage d) by deploying an isolator onthe substrate, followed by the formation of contact points on thesource, drain and gate areas of the transistors.

Furthermore, the process may comprise, additionally, connecting the gateof the first transistor to a doped zone separate from the first dopedzone and forming one of the source and drain of the second transistor,and connecting the gate of the second transistor to the first dopedzone.

In the example considered in the present description, where the sourceof the second transistor is constituted by the second doped zone, thegate of the first MOS transistor is connected to the drain of the secondtransistor, in other words to the third doped zone.

Where the limiter means comprises a diode, the process for manufacturingthe device comprises the following successive stages:

a) preparation in a substrate of a so-called active zone having a firstconductivity type, intended to receive the first transistor and thediode,

b) formation of a first and a second gate above the active zonecorresponding to the first transistor and the diode respectively, thegates being separated from the substrate by a gate insulator,

c) formation of source and drain areas of the first transistor and ofsaid second doped zone, formation of the first doped zone placed betweena channel of the first transistor and the second doped zone, andformation of the third doped zone separated from the first doped zone bythe second doped zone, the source and drain areas and the first dopedzone being formed by self-aligned implantations on the first gate,

d) formation of a conductive layer in contact with the first doped zoneand the second doped zone so as to connect them electrically.

The different doped areas or zones formed during stage c) may be soformed in any order.

The process may be completed, after stage d), by deploying an isolatoron the substrate followed by the formation of contact points on thesource and drain areas and on the third doped zone.

It may additionally comprise the interconnection of the third doped zoneand of the gate of the first transistor.

The device is preferably made on an SOI type substrate, in other words asubstrate having a thin silicon surface layer, insulated by a layer ofoxide buried in a silicon block acting as a support.

The components are in this case formed in the thin surface layer. Hislayer is not generally doped initially. However, the preparation stagea) may comprise a slight doping of the first conductivity type, of allor part of the thin surface layer.

Additionally, the active area may be delimited by local oxidation of thethin surface layer to form field oxide blocks. This surface insulationtechnique is usually known as “LOCOS” (Localised Oxidation of Silicon).The active area may also be delimited by Shallow Trench Isolation.

The active zone is thus completely insulated by the field oxide blocksand by the buried oxide layer.

Other characteristics and advantages of the present invention willemerge more clearly from the following description, with reference tothe appended drawings. This description is given purely by way ofillustration and non-restrictively.

BRIEF DESCRIPTION OF FIGURES

FIG. 1, already described, is an electrical diagram corresponding to adynamic threshold voltage MOS transistor (DTMOS).

FIG. 2, already described, is an electrical diagram of the transistor inFIG. 1, fitted with a current limiter, according to a first polarisationconfiguration of the limiter.

FIG. 3, already described, is an electrical diagram of the transistor inFIG. 1, fitted with a current limiter, according to a secondpolarisation configuration of the limiter.

FIG. 4 shows a first implantation diagram for the manufacture of adevice according to the invention

FIG. 5 is a diagrammatic cross-section of a device according to theinvention along a plane V—V shown in FIG. 4.

FIG. 6 shows a second implantation diagram for the manufacture of adevice according to the invention.

FIG. 7 is a diagrammatic cross-section of a device according to theinvention along a plane VII—VII shown in FIG. 6.

FIG. 8 shows a third implantation diagram for the manufacture of adevice according to the invention.

FIG. 9 is a diagrammatic cross-section of a device according to theinvention along a plane IX—IX shown in FIG. 8.

FIGS. 10 and 11 are electrical diagrams corresponding to anotherembodiment possibility of the device of the invention.

FIG. 12 is an electrical diagram equivalent to that in FIG. 10.

FIG. 13 is a fourth implantation diagram for the manufacture of a deviceaccording to the invention, according to the electrical diagram in FIG.10.

FIG. 14 is a diagrammatic cross-section of a device according to theinvention along a plane XIV—XIV shown in FIG. 13.

FIG. 15 is a fifth implantation diagram for the manufacture of a deviceaccording to the invention, according to the electrical diagram in FIG.10.

FIG. 16 is a sixth implantation diagram for the manufacture of a device,according to the invention according to the electrical diagram in FIG.10.

FIG. 17 is a seventh implantation diagram for the manufacture of adevice according to the invention, according to the electrical diagramin FIG. 10.

DETAILED DESCRIPTION OF MODES FOR IMPLEMENTING THE INVENTION

The following description refers to the manufacture of the device in thesilicon surface layer of an SOI type substrate.

The plane of FIG. 4 corresponds to a view from above of the deviceaccording to a first embodiment.

A continuous line 100 in FIG. 4 represents the limit of the active zone102 defined on the surface layer of silicon.

Outside the zone defined by the line 100, the surface layer of siliconis oxidised so as to isolate the active zone laterally.

A certain number of impurity implantation ranges defined above theactive zone, and described in more detail hereinafter, partly overlapthe oxidised silicon, for implantation pattern design reasons. However,it should be noted that the implanted doping impurities reaching thesilicon oxide which surrounds the active zone, are ineffective and donot modify the isolating electrical character of the oxide.

At least one first P-type implantation is practised in two implantationranges 110, 120, which correspond in particular to the channels of afirst and a second transistor 10 and 20 which it is desired to form.These ranges are shown by a regular broken line in the figure and aredefined, for example, by an aperture in an implantation mask not shown.

As shown previously, these transistors correspond to the DTMOStransistor and to the current limiter transistor in terms of theinvention.

The first implantation is P type in so far as the transistor 10 and 20which it is desired to make are NMOS transistors. The device may howeverbe also made with PMOS transistors. In this case, the first implantationis N type.

The first implantation is followed by the formation of a layer ofinsulator, for example of oxide, then by a layer of gate material, forexample of polycrystalline silicon.

The layers are etched according to a pattern allowing the form andlocation of gates 116 and 126 of the first and second transistorrespectively to be fixed.

It may be seen that the gate 116 of the first transistor has a T shapeat least one branch of which extends beyond the active zone.

The definition of the gates may be followed by the formation of lateralspacers on their sides. These spacers are not shown in FIG. 4 forreasons of clarity.

After the formation of the gates at least one N⁺ type implantation iseffected with a concentration above that of the first implantation. Inthe remainder of the text the symbols N⁺ and P⁺ are used to denoteimplantations or implanted areas of N and P conductivity type with aheavy concentration of doping impurities.

It should be specified that the second implantation may also be P⁺ typewhen the transistors formed a re PMOS transistors.

The second implantation takes place in implantation ranges 130, 140extending on either side of at least one part of each gate 116, 126. Theimplantation ranges 130, 140 are shown in a dot and dash line and aredefined, for example, by apertures in an implantation mask not shown.

During the second implantation are formed, in the active zone, the drain112 and the source 114 of the first transistor and also the drain 122and the source 124 of the second transistor.

The source 124 and the drain 122 correspond respectively to the secondand third doped zones mentioned in the first part of the description.

The N⁺ type zones 112, 114, 122 and 124 do not extend, or only veryslightly, under the gates.

Indeed, the gates act, during implantation, as an implantation mask,with the result that the N⁺ type zones are self-aligned on the gates.

Under the gate 116 of the first transistor 10 there is consequently a Ptype zone resulting from the first implantation. A part of this zonelocated between the source and drain 112, 114 constitutes the channel111 of the first transistor 10.

In the same way, the P type channel 121 of the second transistor 20 islocated under the second gate 126 and between the source and drain 124and 122 of the second transistor.

A third P⁺ type implantation (or, as an alternative N⁺ for PMOStransistors) is effected in a range 150 defined, for example, by animplantation mask not shown.

It may be seen that the implantation range 150 shown in a dual dot anddash line overlaps a part of the gate 116 of the first transistor andcoincides with a part of the P type active zone and extends to thesource 124 of the second transistor.

A part of the gate 116 of the first transistor may thus be used as animplantation mask, so that the doped zone 160 formed during the thirdimplantation is self-aligned on this gate.

The doped P⁺ type zone 160 corresponds to the first doped zonepreviously mentioned and is so designated in the remainder of the text.It constitutes a substrate point for the first transistor 10.

A self-aligned silicidation on the gates is thus practised. It allows alayer of silicide to be formed on the active zone and on the gates. Theessential function of this layer of silicide is to form an electricalconnection by ohmic contact between the first doped zone 160 and thesource 124 of the second transistor.

The layer of silicide, for example of TiSi₂, or CoSi₂, not shown in FIG.4, may be formed by depositing a layer of titanium or of cobalt,followed by heat treatment.

After silicidation, the deposit and planarisation of electricalinsulator material is carried out allowing the device to be protected.The electrical insulator material is for example a silicon oxide.

The electrical insulator material is then etched locally, according to apre-set pattern, to form access passages to the components and to makecontact points on them.

Lastly, after filling the passages with a conductive material, such asmetal, there are formed, on the surface of the electrical insulatormaterial, conductive interconnection tracks connected to the contactpoints.

In FIG. 4, the references 113, 115, 123, 117, 127 denote contact pointsconnected to the drain and to the source of the first transistor, to thedrain of the second transistor, and to the gates of the first and secondtransistors respectively.

The references 173, 175, 187 denote metal interconnection tracks, forexample of Al, Ti or W, connected to the contact points 113, 115 and127, to connect them possibly to other components not shown.

The reference 190 denotes an interconnection track which connects thecontact point 117 of the gate of the first transistor to the contactpoint 123 of the drain 122 of the second transistor.

It may also be seen in FIG. 4 that the contact points 117, 127 on thegates are made outside the active zone 102, in other words above thesilicon oxide which surrounds the active zone.

FIG. 5 is a diagrammatic cross-section of the device obtained accordingto the diagram in FIG. 4 and along the plane V—V shown in FIG. 4.

The device is made in an SOI type substrate including a solid part 1 ofsilicon, a buried layer 2 of silicon oxide and a thin surface layer 3 ofsilicon. For reasons of convenience, the scales of thickness of thedifferent layers and parts of the device are not respected.

In the surface layer of silicon, an active zone 102 is delimited byblocks of silicon oxide 103 which extend to the buried oxide layer. Theactive zone is therefore insulated relative to the solid part 1 of thesubstrate and possibly other active zones not shown, defined in the samesurface layer.

In the active zone, there may be distinguished, in order, from left toright in the figure, the P type channel 111 of the first transistor 10,the first P⁺ type doped zone 160 in contact with the channel 111, thesource 124 of the second N⁺ type transistor 11, in contact with thefirst doped zone, the P type channel 121 of the second transistor 11,then the N⁺ type drain 122 of the second-transistor 11.

Above the channel 111 of the first transistor and above the channel 121of the second transistor may be distinguished the gates 116 and 126 ofthe first and second transistors respectively. The gates, for example ofpolycrystalline silicon, are separated from the surface layer of silicon3 by a very thin layer of silicon oxide 4.

On the parts of the active zone not covered by the gates, in the sameway as on the gates, the presence may be noted of a layer of titanium orcobalt silicide 180. The layer of silicide establishes in particular anohmic electrical contact between the first doped area 160 and the source124 of the second transistor.

Before silicidation, lateral insulating spacers 181 are formed on thelateral sides of the gates, by deposit of a layer of silicon oxide ornitride then by anisotropic etching of this layer.

The essential function of the lateral spacers 181 is to prevent ashort-circuit between the gates, the source areas, and the drain areas,during formation of the layer of silicide 180.

Possibly, the lateral spacers may be formed before implantation of thesource and drain areas of the transistors, and also act, just like thegates, as an implantation mask for these areas.

An insulation layer 183 is formed by deposit then by planarisation of amaterial such as silicon oxide. The layer 183, the surface of which isplane coats the gates and covers the silicide layer 180.

FIG. 5 also shows the contact point 123 which is presented in the formof a well passing through the insulation layer 183 to reach the layer ofsilicide above the drain 122 of the second transistor. The well isfilled with an electrical conductive material such as W or Ti whichallows the drain to be electrically connected to the interconnectiontrack 190.

FIGS. 4 and 5 described above correspond to the manufacture of a dynamicthreshold voltage NMOS transistor.

A PMOS transistor of this type may also be made by replacing the N⁺, P,P⁺ type areas by P⁺, N and N⁺ areas respectively.

Furthermore, it may be seen that making the transistor according toFIGS. 4 and 5 corresponds to the electrical diagram in FIG. 2 previouslydescribed.

FIG. 6 is a view from above of an implantation diagram for making aDTMOS transistor according to a variant corresponding to the electricaldiagram in FIG. 3.

A large number of elements in FIG. 6 are identical to correspondingelements in FIG. 5. These elements carry the same references and adetailed description of them is not given here. Reference may be made tothe preceding description.

It may be seen that a contact point 125 is formed in an area overlappingthe first doped zone 160 and the source zone 124 of the secondtransistor. It is connected furthermore to the contact point 127 of thegate of the second transistor by an interconnection track 185.

It should however be noted in this respect that the contact point 125constitutes essentially a contact point for the substrate or, moreexactly, for the channel of the first transistor.

The contact point 125 and the interconnection track 185 can also be seenin FIG. 7 which is a cross-section of a device manufactured inaccordance with the implantation diagram in FIG. 6, seen along the planeVII—VII shown in this figure.

The contact point 125 overlaps to an approximately equal extent thefirst doped zone 160 and the source area 124. The position of thecontact point is not critical however. Indeed, since a conductive linkexists between the zones mentioned above, by virtue of the layer ofsilicide 180, it is sufficient for the contact point 125 to come intocontact with the silicide layer portion 180 which coats these zones.

A device variant corresponding to the same electrical diagram may alsobe made along the implantation plane in FIG. 8.

This plane is distinguished from that in FIG. 6 in that a single contactpoint 128 replaces the contact point of the gate of the secondtransistor, the contact point connected to the source and to the firstdoped zone, as well as the interconnection track connecting them.

As is shown in cross-section in FIG. 9, the contact point 128 partlyoverlaps the gate 126 and the source 124 of the second transistor.

The conductive material of the contact point 128 connects electricallythe gate 126 and more exactly the silicide layer portion which coats thegate, to the silicide layer portion which coats the source zone 124 andthe first doped zone 160. The contact point 128 may possibly be cappedwith a metal terminal 189.

Comparing this structure with that in FIGS. 6 and 7, it may be notedthat the contact point 127 may be omitted, as may be the interconnectiontrack 185.

The device in FIGS. 8 and 9 may therefore be made more compactly thanthe devices previously described.

FIG. 10 is an electrical diagram corresponding to a second possibledesign of the device of the invention wherein the second transistor isreplaced by a diode 30.

The anode 32 of the diode 30 is connected to the gate 16 of the firsttransistor 10 and the cathode 34 of the diode is connected to thesubstrate of the transistor 10, more exactly to its channel. The drainand source terminals of the transistor 10 are still identified by thereferences 12 and 14. A terminal of the substrate, or more exactly ofthe transistor channel, carries the reference 11 by analogy with FIGS. 1to 3.

The diagram in FIG. 10 corresponds to that of a device constructedaround an NMOS type transistor.

FIG. 11 gives for information only the electrical diagram intended for aPMOS transistor. It may be seen that, in this case, the cathode 34 ofthe diode is connected to the gate of the transistor and the anode 32 tothe substrate (channel).

The diode 30, the essential function of which is to limit the currentpassing through the substrate point of the transistor, is connected inseries with the “diodes” corresponding to the substrate-source andsubstrate-drain junctions of the transistor.

For the device in FIG. 10, using an NMOS transistor, an equivalentelectrical diagram is given in FIG. 12.

In this figure, the references 40 and 50 denote the substrate-drain“diode” and the substrate-source “diode” of the transistor respectively.The references 11, 12, 14 and 16 denote substrate, drain, source andgate terminals of the transistor respectively. The letters V_(b), V_(d),V_(s) and V_(g) carried in the figure in the vicinity of the terminalsof the electrical diagram are used in the remainder of the text todenote the substrate, drain, source and gate voltages.

V_(t) further denotes the threshold voltage of the transistor. It mayalso be expressed by the following formula:

V _(t) =V _(fb)+2φ_(f)+γ{square root over (2φ_(f) −V _(bs))}  (1)

where V_(bs)=V_(b)−V_(s) and where V_(fb) is the flat band voltage.

To determine the threshold voltage of the DTMOS, when the currentlimiter means is a diode, the substrate potential V_(b) in the proposedstructure should be calculated and its expression conveyed in theequation (1). The current equation of a diode (or junction) passedthrough by a current I at a low rate of injection is:$I = {I_{0}\left\lbrack {{\exp \left( \frac{V}{{nU}_{t}} \right)} - 1} \right\rbrack}$

In this expression, V is the voltage applied to the terminals of thediode, n its ideality factor, Ut=kT/q is the thermal potential, q theelectron charge, k the Boltzmann constant, T the temperature, I₀ thedark current.

The current equation of the diode 30 acting as limiter is thus:$I_{1} = {I_{01}\left\lbrack {{\exp \left( \frac{V_{g} - V_{b}}{{nU}_{t}} \right)} - 1} \right\rbrack}$

The current equation of the substrate-source “diode” 50 is:$I_{2} = {I_{02}\left\lbrack {{\exp \left( \frac{V_{b} - V_{s}}{{nU}_{t}} \right)} - 1} \right\rbrack}$

and the current equation of the substrate-drain “diode” 40 is:$I_{3} = {I_{02}\left\lbrack {{\exp \left( \frac{V_{b} - V_{d}}{{nU}_{t}} \right)} - 1} \right\rbrack}$

I₀₁, I₀₂ are respectively the dark currents of the diodes mentionedabove.

The dark current of the diode acting as limiter is presumed differentfrom that of the substrate-source and substrate-drain junctions. Withreference to FIG. 11, it may be seen that the current passing throughthe clamping diode is equal to the sum of the currents passing throughthe substrate-drain and substrate-source diodes i.e.:

I ₁ =I ₂ +I ₃

The solution of this equation allows the substrate potential to beexpressed as a function of the gate potential:$v_{bs} = {{nU}_{t}{\ln \left\lbrack \frac{{2I_{02}} - I_{01} + {\sqrt{\left( {I_{01} - {2I_{02}}} \right)^{2} + {4I_{01}I_{02}{\exp \left( \frac{V_{gs}}{{nU}_{t}} \right)}}}\left( {1 + {\exp \left( {- \frac{V_{ds}}{{nU}_{t}}} \right)}} \right)}}{2{I_{02}\left( {1 + {\exp \left( {- \frac{V_{ds}}{{nU}_{t}}} \right)}} \right)}} \right\rbrack}}$

in this expression it may be noted that:

V _(gs) =V _(g) −V _(s) and V _(ds) =V _(d) −V _(s).

The expression of V_(bs) obtained conveyed in the equation (1) allowsthe variation in threshold voltage of the DTMOS transistor with thecurrent clamping diode to be calculated as a function of the voltageapplied to its gate.

By way of example, if the clamping diode is dimensioned in such a way asto give:

I ₀₁=2I ₀₂

the substrate potential becomes:$V_{bs} = {\frac{V_{gs}}{2} - {\frac{{nU}_{t}}{2}{\ln \left\lbrack {1 + {\exp \left( {- \frac{V_{ds}}{{nU}_{t}}} \right)}} \right\rbrack}}}$

When the difference in potential V_(ds) exceeds a few times U_(t)(during normal operation of the transistor), the simple relation isobtained: $V_{bs} \approx \frac{V_{gs}}{2}$

The DTMOS threshold voltage with current limiting by diode may thereforebe approximated by:$V_{t} = {V_{fb} + {2\varphi_{f}} + {\gamma \sqrt{{2\varphi_{f}} - \frac{V_{gs}}{2}}}}$

FIG. 13 shows an implantation diagram for the manufacture of a devicecorresponding to the electrical diagrams in FIGS. 10 and 12.

By virtue of a great number of similarities with FIGS. 4, 6 and 8,identical or equivalent elements are identified with the same referencesso that reference may be made to the preceding description.

The process for manufacturing the transistor 10 and the diode 30 isapproximately the same as the process of manufacturing the firsttransistor 10 and the second transistor 11 in FIG. 4.

Indeed, although in the case of the present embodiment, the currentlimiting means are a diode, the gate 126 is retained.

This gate allows a second N⁺ type doped zone 124 a to be separated froma third P⁺ type doped zone 122 a.

It may be seen that the second and third doped zones correspond, bytheir location, to the source and drain zones of the transistor 20 whichcan be seen in FIGS. 4, 6 and 8.

The second and third N⁺ and P⁺ type doped zones are implantedrespectively in implantation ranges 140 a, 140 b defined by implantationmasks not shown.

Same conductivity type zones may be made concomitantly.

Thus, the second doped zone 124 a may be implanted simultaneously withthe source and drain zones 112, 114 of the transistor 10 whereas thethird doped zone 122 a may be implanted simultaneously with the firstdoped zone 160.

It may be seen that the implantation ranges 140 a and 140 b partlyoverlap the second gate 126 which also acts as an implantation mask. Thesecond and third doped zones are thus self-aligned on the second gate126.

Under the gate 126 is a fourth P (or N) type doped zone 121 whichconnects the second and third doped zones.

The fourth doped zone is P (or N) type by virtue of the initialpreparation of the substrate. It is protected by the gate 126 duringimplantations of the second and third doped zones.

The fourth P (or N) type doped zone extends the third doped zone 122 a,also of P⁺ type, but the doping concentration of which is higher thanthat of the fourth zone.

Thus the current clamping diode 30 is formed by the N+/P junctionbetween the second doped zone (or P+/N) 124 a and the third doped zone122 a extended by the fourth doped zone 121.

The second and third doped zones form the terminals of the diode.

Although the gate 126 above the fourth doped zone can be left at afloating potential, FIG. 13 shows an interconnection line 185 whichconnects a connection point 127 in contact with the gate 126 and aconnection point 125 in contact with the first and second doped zonesrespectively.

FIG. 14 is a transverse cross-section of the device corresponding toFIG. 13, along a cross-section plane XIV—XIV also shown in FIG. 13.Identical or similar parts to those in FIGS. 5, 7, 9 and 14 areidentified with the same references. Reference may be made in thisrespect to the preceding description.

FIG. 14 shows that the first and second doped zones are coated by asilicide layer portion 180 with the result that they are at the sameelectrical potential. The silicide layer in fact provides an electricalohmic contact between these zones. Thus, the connection point 125 incontact with the first and second doped zones, which is shown in aposition overlapping these zones, and which is in contact with theportion of the silicide layer which coats said zones, could be offsetabove one only of the first and second doped zones.

FIG. 14 also highlights a particular role of the second gate 126 and ofits lateral spacers. This role is to isolate the silicide layer portion180 which coats the first and second doped zones 160, 124 a of theportion of this layer which coats the third doped zone 122 a.

The references 123 and 190 show a contact point on the third doped zone122 a and an interconnection track, which can also be seen in FIG. 13,which connects this zone to the transistor gate.

The device described above may also be made along an implantation planein accordance with FIG. 15.

FIG. 15 is distinguished from FIG. 13 in that a contact point 128intended for the first and second doped zones is positioned so as tooverlap the second doped zone and the gate 126 of the diode.

Thus, the conductive material of the contact point electrically connectsthe gate to the first and second doped zones.

Such an arrangement, comparable to that in FIG. 8, allows thecorresponding interconnection 185 which can be seen in FIG. 13 to beomitted, and thus the device to be made more compact.

Another embodiment variant of the device is illustrated by FIG. 16.

In this figure it may be seen that the contact point 127 of the gate isconnected to the contact point 123 of the third doped zone by anextension of the interconnection track 190.

Lastly, a final embodiment variant of the device, illustrated by FIG. 17and approximately equivalent to the previous one, makes it possible tosave on one specific contact point for the gate and the extension of theinterconnection track 190.

Indeed, a contact point 189, common to the gate 126 and to the thirddoped zone 122 a, is arranged so as to overlap these two parts andconnect them electrically.

The contact point 189 is furthermore connected to the contact point 117of the gate of the transistor by means of an interconnection 190 a.

DOCUMENTS CITED

(1) J. P. Colinge, “An SOI Voltage-Controlled Bipolar-MOS Device”, IEEETransactions on Electron devices, volume ED-34, no. 4, p. 845, 1987.

(2) M. Matloubian, “Analysis of Hybrid-Mode Operation of SOI MOSFET's”,IEEE International SOI Conference Proceedings, p. 106, 1993.

(3) F. Assaderaghi et al., “A Dynamic Threshold Voltage MOSFET (DTMOS)for Ultra-Low Voltage Operation”, International Electron Devices MeetingTechnical Digest, p. 809, 1994.

(4) Y. P. Tsividis, “Operation and Modeling of the MOS Transistor”,MacGraw-Hill Book Company, 1987.

What is claimed is:
 1. A semiconductor device formed on a substrate,comprising: a first dynamic threshold voltage MOS transistor having agate and a channel of a first conductivity type; a first doped zone ofthe first conductivity type coupled to the channel of said first MOStransistor; and a transistor or diode type current limiter coupledbetween the gate of said first MOS transistor and said first doped zone,said current limiter comprising a second doped zone of a secondconductivity type physically disposed against and in ohmic connectionwith said first doped zone.
 2. The device according to claim 1, whereinthe transistor or diode type current limiter comprises a secondtransistor, the second doped zone embodying the source of said secondtransistor.
 3. The device according to claim 2, wherein the secondtransistor includes a gate coupled to a gate polarization terminal. 4.The device according to claim 2, wherein the second transistor has agate coupled to said second doped zone.
 5. The device according to claim4, further comprising a terminal that is coupled to the gate of saidsecond transistor and to the second doped zone.
 6. The device accordingto claim 4, wherein a drain of said second transistor is coupled to thegate of the first MOS transistor.
 7. The device according to claim 1,wherein the transistor or diode type current limiter comprises a diode,the second doped zone embodying a first terminal of the diode and athird doped zone of a conductivity type opposite that of theconductivity type of the second doped zone embodying a second terminalof the diode.
 8. The device according to claim 7, further comprising afourth doped zone disposed between the second and third doped zones,said fourth doped zone having the same conductivity type as theconductivity type of either the second or third zones.
 9. The deviceaccording to claim 7, wherein the third doped zone is coupled to thegate of the first MOS transistor.
 10. The device according to claim 8,wherein the diode comprises a gate extending over the fourth doped zone.11. The device according to claim 10, wherein said diode gate is coupledto one of the diode terminals.